Memory controller is incorporated in or provided outside of an arithmetic processing apparatus such as a processor, and control access to a main memory such as a dynamic random access memory (DRAM).
Memory modules incorporating a DRAM controller chip, such as a hybrid memory cube (HMC), is under development to be the successor of conventional DRAM modules, used as a main memory of an information processing apparatus. The memory module is connected to a memory controller on a processor side through a high-speed serial bus. The high-speed serial bus includes a transmission serial bus and a reception serial bus. A request command requesting an access from the processor side is transmitted to the memory module through the transmission serial bus. When the request command is a write command, a write request command is transmitted through the transmission serial bus, together with write data. When the request command is a read command, a read request command is transmitted through the transmission serial bus. Then, read data is read out from the memory module, and after a latency time, the read data is returned to the processor side as a reply through the reception serial bus.